Optimizing DSP Circuits by a New Family of Arithmetic Operators

dc.contributor.author	Hormigo-Aguilar, Javier
dc.contributor.author	Villalba-Moreno, Julio
dc.date.accessioned	2014-11-19T13:12:03Z
dc.date.available	2014-11-19T13:12:03Z
dc.date.created	2014-11-04
dc.date.issued	2014-11-19
dc.identifier.uri	http://hdl.handle.net/10630/8443
dc.description	IEEE Signal Processing Society	es_ES
dc.description.abstract	A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators may decrease significantly the size of the circuits required for most applications. That means a simultaneous reduction of area, delay and power consumption.	es_ES
dc.description.sponsorship	Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.	es_ES
dc.language.iso	eng	es_ES
dc.rights	info:eu-repo/semantics/openAccess	es_ES
dc.subject	Aritmética computacional	es_ES
dc.subject.other	Computer Arithmetic	es_ES
dc.subject.other	DSP	es_ES
dc.subject.other	Rounding to nearest	es_ES
dc.subject.other	Real number representation	es_ES
dc.title	Optimizing DSP Circuits by a New Family of Arithmetic Operators	es_ES
dc.type	info:eu-repo/semantics/conferenceObject	es_ES
dc.centro	E.T.S.I. Industrial	es_ES
dc.relation.eventtitle	48- Asilomar Conference on Signals, Systemas and Computers	es_ES
dc.relation.eventplace	Asilomar Conference ground, Pacific Grove, California, USA	es_ES
dc.relation.eventdate	2-11-2014 a 5-11-2014	es_ES