Optimizing DSP Circuits by a New Family of Arithmetic Operators
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Fecha
2014-11-19 -
Palabras clave
Aritmética computacional -
Resumen
A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators may decrease significantly the size of the circuits required for most applications. That means a simultaneous reduction of area, delay and power consumption.