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Scalability Analysis of Signatures in Transactional Memory Systems
dc.contributor.author | Quislant-del-Barrio, Ricardo | |
dc.contributor.author | Gutiérrez-Carrasco, Eladio Damián | |
dc.contributor.author | Plata-González, Óscar Guillermo | |
dc.date.accessioned | 2014-10-29T08:01:54Z | |
dc.date.available | 2014-10-29T08:01:54Z | |
dc.date.created | 2014-10-22 | |
dc.date.issued | 2014-10-29 | |
dc.identifier.uri | http://hdl.handle.net/10630/8330 | |
dc.description.abstract | Signatures have been proposed in transactional memory systems to represent read and write sets and to decouple transaction conflict detection from private caches or to accelerate it. Generally, signatures are implemented as Bloom filters that allow unbounded read/write sets to be summarized in bounded space at the cost of false conflict detection. It is known that this behavior has great impact in parallel performance. In this work, a scalability study of state-of-the-art signature designs is presented, for different orthogonal transactional characteristics, including contention, length, concurrency and spatial locality. This study was accomplished using the Stanford EigenBench benchmark. This benchmark was modified to support spatial locality analysis using a Zipf address distribution. Experimental evaluation on a hardware transactional memory simulator shows the impact of those parameters in the behavior of state-of-the-art signatures. | es_ES |
dc.description.sponsorship | Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. | es_ES |
dc.language.iso | eng | es_ES |
dc.subject | Ingeniería de ordenadores | es_ES |
dc.subject.other | Hardware transactional memory | es_ES |
dc.subject.other | Bloom filter | es_ES |
dc.subject.other | Conflict detection | es_ES |
dc.subject.other | Locality | es_ES |
dc.subject.other | Multiset | es_ES |
dc.subject.other | Asymmetric | es_ES |
dc.subject.other | Signatures | es_ES |
dc.title | Scalability Analysis of Signatures in Transactional Memory Systems | es_ES |
dc.type | conference output | es_ES |
dc.centro | E.T.S.I. Industrial | es_ES |
dc.relation.eventtitle | SBAC-PAD 2014 | es_ES |
dc.relation.eventplace | Paris, France | es_ES |
dc.relation.eventdate | 22 a 24 de octubre de 2014 | es_ES |
dc.departamento | Arquitectura de Computadores | |
dc.rights.accessRights | open access | es_ES |