We propose a floating–point representation to deal
efficiently with arithmetic operations in codes with a balanced
number of additions and multiplications for FPGA devices. The
variable shift operation is very slow in these devices. We propose
a format that reduces the variable shifter penalty. It is based on
a radix–64 representation such that the number of the possible
shifts is considerably reduced. Thus, the execution time of the
floating–point addition is highly optimized when it is performed
in an FPGA device, which compensates for the multiplication
penalty when a high radix is used, as experimental results have
shown. Consequently, the main problem of previous specific highradix
FPGA designs (no speedup for codes with a balanced
number of multiplications and additions) is overcome with our
proposal. The inherent architecture supporting the new format
works with greater bit precision than the corresponding single
precision (SP) IEEE–754 standard.