Listar AC - Contribuciones a congresos científicos por título
Mostrando ítems 46-65 de 106
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Hardware support for scratchpad memory transactions on GPU architectures
Villegas Fernández, Alejandro; Asenjo-Plaza, Rafael
; González-Navarro, María Ángeles; Plata-González, Óscar Guillermo; Ubal, Rafael; Kaeli, David[et al.] (Springer, 2017-08-29)
Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL ... -
Heuristics for Longest Edge Selection in Simplicial Branch and Bound
Herrera, Juan F.R.; Casado, Leocadio G.; Hendrix, Eligius María Theodorus; García-Fernández, Inmaculada (2015-07-06)
Simplicial partitions are suitable to divide a bounded area in branch and bound. In the iterative re nement process, a popular strategy is to divide simplices by their longest edge, thus avoiding needle-shaped simplices. ... -
High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.
Dynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is ... -
HPC Accelerators with 3D Memory
Ujaldon-Martínez, Manuel (2016-09-13)
After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have con- quered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. ... -
iDA: Preservando el acceso a bases de datos a muy largo plazo.
El proyecto iDA (Immortal Database Accesss) tiene como objetivo el ofrecer una visión general de las posibilidades tecnológicas para la preservación de los sistemas informáticos desmantelados (decommissioned) y los datos ... -
Implementaciones paralelas para un problema de control de inventarios de productos perecederos
Gutiérrez-Alcoba, Alejandro; Hendrix, Eligius María Theodorus; García-Fernández, Inmaculada; Ortega, Gloria L. (2015-10-05)
En este trabajo se analizan y eval uan dos implementaciones de un algoritmo de optimizaci on para un problema de control de inventarios de productos perecederos. Las implementaciones se han llevado a cabo utilizando ... -
Improvements in Hardware Transactional Memory for GPU Architectures
Villegas Fernández, Alejandro; Asenjo-Plaza, Rafael; González-Navarro, María Ángeles; Plata-González, Óscar Guillermo (2016-07-20)
In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of ... -
Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ... -
Improving Signatures by Locality Exploitation for Transactional Memory
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Plata-González, Óscar Guillermo; López-Zapata, Emilio (IEEE, 2009)
Writing multithreaded programs is a fairly complex task that poses a major obstacle to exploit multicore processors. Transactional Memory (TM) emerges as an alternative to the conventional multithreaded programming to ... -
Improving Transactional Memory Performance for Irregular Applications
Pedrero-Luque, Manuel; Gutiérrez-Carrasco, Eladio Damián; Romero-Montiel, Sergio; Plata-González, Óscar Guillermo (2015-06-11)
Transactional memory (TM) offers optimistic concurrency support in modern multicore archi- tectures, helping the programmers to extract parallelism in irregular applications when data dependence information is not available ... -
Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Zapata, Emilio L.; Plata-González, Óscar Guillermo (Springer International Publishing, 2016-08-24)
Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation ... -
An Introduction to Intel Threading Building Blocks and its Support for Heterogeneous Programming
Asenjo-Plaza, Rafael; Cownie, Jim; Fedotov, Aleksei (2018-03-12)
Due to energy constraints, high performance computing platforms are becoming increasingly heterogeneous, achieving greater performance per watt through the use of hardware that is tuned to specific computational kernels ... -
Irrevocabilidad Relajada para Memoria Transaccional Hardware
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Zapata, Emilio L.; Plata-González, Óscar Guillermo (2016-09-20)
Los sistemas comerciales que ofrecen memoria transaccional (TM) implementan un sistema hardware best-effort (BE-HTM) con limitaciones. Es necesario programar un fallback software basado en cerrojos para asegurar el progreso ... -
Localizando partículas en un fluido a partir de holografías y computación de altas prestaciones
Ortega, Gloria L.; Lobera, Julia; García-Fernández, Inmaculada; Arroyo, Maria del Pilar; Garzón, Ester M. (2014-09-24)
La tomografía se ha introducido recientemente en la velocimetría de fluidos para proporcionar información en tres dimensiones de la localización de partículas en el seno de fluidos. En concreto, algunos trabajos previos ... -
Low-textured regions detection for improving stereoscopy algorithms
Ibarra-Delgado, Salvador; Ramos-Cózar, Julián; González-Linares, José María; Gómez Luna, Juan; Guil-Mata, Nicolás (2014-07-29)
The main goal of stereoscopy algorithms is the calculation of the disparity map between two frames corresponding to the same scene, and captured simultaneously by two different cameras. The different position (disparity) ... -
Memoria Transaccional Hardware en Memoria Local de GPU
Villegas Fernández, Alejandro; González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Plata-González, Óscar Guillermo (2015-09-25)
Los aceleradores gráficos (GPUs) se han convertido en procesadores de prop ́osito general muy populares para el cómputo de aplicaciones que presen- tan un gran paralelismo de datos. Su modelo de ejecución SIMT (Single ... -
Memoria Transaccional Software en Procesadores CPU+GPU Heterogéneos
González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Plata-González, Óscar Guillermo; Villegas Fernández, Alejandro (2018-09-19)
En los procesadores multi-núcleo, la memoria transaccional (TM) ha aparecido como una alternativa prometedora a las técnicas basadas en cerrojos para garantizar exclusión mutua y está siendo incluida como parte de procesadores ... -
Modelling vessel fleet composition for maintenance operations at offshore wind farms
Gutiérrez-Alcoba, Alejandro; García-Fernández, Inmaculada; Ortega López, Gloria; Hendrix, Eligius María Theodorus (2018-12-20)
Chartering a vessel fleet to support maintenance operations at offshore wind farms (OWF's) constitutes one of the major costs of maintaining this type of installations. Literature describes deterministic optimization models ... -
Multimodal Human Pose Feature Fusion for Gait Recognition.
Cubero, Nicolás; Castro Payán, Francisco Manuel; Ramos-Cózar, Julián; Guil-Mata, Nicolás; Marín Jiménez, Manuel Jesús (2023)
Gait recognition allows identifying people at a distance based on the way they walk (i.e. gait) in a non-invasive approach. Most of the approaches published in the last decades are dominated by the use of silhouettes or ... -
Multiset Signatures for Transactional Memory
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Plata-González, Óscar Guillermo; López-Zapata, Emilio (ACM, 2011)
Transactional Memory (TM) systems must record the memory locations read and written (read and write sets) by concurrent transactions in order to detect conflicts. Some TM implementations use signatures for this purpose, ...