Listar AC - Contribuciones a congresos científicos por título
Mostrando ítems 18-37 de 106
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C++ for Heterogeneous Programming: oneAPI (DPC++ and oneTBB)
Reinders, James; Voss, Michael J.; Reble, Pablo; Asenjo-Plaza, Rafael
(2020-11-19)
This tutorial provides hands-on experience programming CPUs, GPUs and FPGAs using a unified, standards-based programming model: oneAPI. oneAPI includes a cross-architecture language: Data Parallel C++ (DPC++). DPC++ is an ... -
CodSim 2.0: Un Laboratorio Virtual para la Enseñanza de las Codificaciones de Datos
Pérez-Trabado, Guillermo; Gutiérrez-Carrasco, Eladio Damián (SARTECO, 2021-09)
Este artículo presenta la herramienta CodSim 2.0, un simulador de codificaciones de datos a nivel físico, dirigido a estudiantes de asignaturas de redes de computadores en grados en ingeniería Informática o Electrónica. El ... -
Computer architecture simulation on the server-side for online evaluation purposes
Due to the global COVID19 pandemic, in the last few months there has been a dramatic change in the educational context where lecturers around the world has forced to solve academic problems that immediately before this ... -
Control y mejora de la coordinación entre asignaturas de una titulación universitaria
(2015-06-17)Entre las múltiples exigencias que impone el EEES, la mejora de la coordinación entre las asignaturas de una titulación es una de las que más preocupan, y se ha convertido en uno de los temas de debate más vivos en ... -
CUVLE: Variable-Length Encoding on CUDA
Fuentes-Alventosa, Antonio; Gómez-Luna, Juan; González-Linares, José María; Guil-Mata, Nicolás (2014-10-14)
Data compression is the process of representing information in a compact form, in order to reduce the storage requirements and, hence, communication bandwidth. It has been one of the critical enabling technologies for ... -
Digit recurence division under HUB format
Villalba-Moreno, Julio (2016-07-21)
Half-Unit-Biased format is based on shifting the representation line of the binary numbers by half Unit in the Last Place. The main feature of this format is that the round to nearest is carried out by a simple truncation, ... -
Diseño del compilador de la máquina virtual inmortal iVM
Gutiérrez-Carrasco, Eladio Damián; Romero-Montiel, Sergio; Plata-González, Óscar Guillermo (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2022-09-21)
Conservar la información digital durante mucho tiempo es difı́cil, incluso cuando se utiliza un medio de almacenamiento pasivo duradero, como una pelı́cula fotográfica almacenada en las condiciones adecuadas. En dicho ... -
DNA Sequences Alignment in Multi-GPUs: Energy Payoff on Speculative Executions
Pérez-Serrano, Jesús; Sandes, Edans; Melo, Alba; Ujaldon-Martínez, Manuel (2017-05-30)
We present a performance per watt analysis of CUDAlign 4.0, a parallel strategy to obtain the optimal alignment of huge DNA se- quences in multi-GPU platforms using the exact Smith-Waterman method. Speed-up factors and ... -
Efficient Floating-Point Representation for Balanced Codes for FPGA Devices
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Corbera-Peña, Francisco Javier; González, Mario; López-Zapata, Emilio (2013-10-30)
We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ... -
Efficient OpenCL-based concurrent tasks offloading on accelerators
Lázaro-Muñoz, Antonio J.; González-Linares, José María; Gómez-Luna, Juan; Guil-Mata, Nicolás (Procedia Computer Science, 2017)
Current heterogeneous platforms with CPUs and accelerators have the ability to launch several independent tasks simultaneously, in order to exploit concurrency among them. These tasks typically consist of data transfer ... -
End-to-end Incremental Learning
Castro Payán, Francisco Manuel; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolás; Schmid, Cordelia; Alahari, Karteek (2018-07-06)
Although deep learning approaches have stood out in recent years due to their state-of-the-art results, they continue to suffer from (catastrophic forgetting), a dramatic decrease in overall performance when training with ... -
Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture
Villegas Fernández, Emilio; Villegas Fernández, Alejandro; González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Ukidave, Yash; Plata-González, Óscar Guillermo[et al.] (2016-09-07)
Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of ... -
Entropy-based High Performance Computation of Boolean SNP-SNP Interactions Using GPUs
Riveros, Carlos; Ujaldon-Martínez, Manuel; Moscato, Pablo (2014-05-02)
It is being increasingly accepted that traditional statistical Single Nucleotide Polymorphism (SNP) analysis of Genome-Wide Association Studies (GWAS) reveals just a small part of the heritability in complex diseases. ... -
Evaluación del consumo energético de la memoria transaccional en procesadores heterogéneos
Villegas Fernández, Emilio; Villegas Fernández, Alejandro; González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Plata-González, Óscar Guillermo (2016)
Actualmente existe una enorme cantidad de dispositivos y sistemas, como ordenadores portátiles y teléfonos móviles, que dependen de una batería para su funcionamiento. Como consecuencia, el hardware que incorporan debe ser ... -
Evaluation of CNN architectures for gait recognition based on optical flow maps
Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolás; López-Tapia, S.; Pérez de la Blanca, N. (2017)
This work targets people identification in video based on the way they walk (\ie gait) by using deep learning architectures. We explore the use of convolutional neural networks (CNN) for learning high-level descriptors ... -
Exploiting Vector Extensions to Accelerate Time Series Analysis.
Quislant-del-Barrio, Ricardo; Fernández-Vega, Iván; Serralvo, Eduardo; Gutiérrez-Carrasco, Eladio Damián; Plata-González, Óscar Guillermo (SARTECO, 2022-09-21)
Time series analysis is an important research topic and a key step in monitoring and predicting events in many fields. Recently, the Matrix Profile method, and particularly two of its Euclidean-distance-based implementations ... -
Explotando el nuevo módulo OpenCL de Intel TBB
Romero, José Carlos; Villegas Fernández, Alejandro; González-Navarro, María Ángeles; Rodríguez-Moreno, Andrés; Asenjo-Plaza, Rafael (2018-07-20)
Este artículo tiene como objetivo contribuir al desarrollo de la programación paralela trabajando en una de las herramientas desarrolladas por Intel: Intel Threading Building Blocks (Intel TBB). Hemos implementado una ... -
Expressing Heterogeneous Parallelism in C++ with Threading Building Blocks
Reinders, James; Voss, Michael J.; Reble, Pablo; Asenjo-Plaza, Rafael (2017-12-18)
Due to energy constraints, high performance computing platforms are becoming increasingly heterogeneous, achieving greater performance per watt through the use of hardware that is tuned to specific computational kernels ... -
A first step to accelerating fingerprint matching based on deformable minutiae clustering
(2018-07-12)Fingerprint recognition is one of the most used biometric methods for authentication. The identification of a query fingerprint requires matching its minutiae against every minutiae of all the fingerprints of the database. ... -
Floating Point Square Root under HUB Format
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ...