The focus of this article is to present a novel crypto-accelerator architecture for a resource constrained
embedded system that utilizes elliptic curve cryptography (ECC). The architecture is
built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA)
attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient
hardware resource utilization for the point multiplication process over GF(2m). This includes the use
of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of
Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined
architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified
using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed
BEC accelerator offers significant performance improvements compared to existing solutions. The
obtained throughput over area ratio for GF(2233) on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx
FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point
multiplication operation on the Virtex-7 device is 19.61 μs. These findings indicate that the proposed
architecture has the potential to address the challenges posed by resource-constrained embedded
systems that require high throughput and efficient use of available resources.
