A frequency locked loop (FLL) for phase noise reduction of wideband voltage controlled oscillators is proposed. The key building block of the system is a low noise (−160 dBV/Hz) and high sensitivity (22 V/GHz) delay line frequency discriminator with 5–8 GHz coverage, which makes use of a high performance multilayer hybrid. The authors derive closed-form, universal design equations for the maximum noise reduction and stability of the FLL circuitry. Application of the proposed technique to a state-of-the-art voltage controlled oscillator operating in the 5–8 GHz band yields a phase noise reduction of 8–10 dB at 100 kHz and 5 dB at 1 MHz off the carrier, which shows the results are in good agreement with the simulated results; so phase noise better than −107 dBc/Hz at 100 kHz and better than −123.5 dBc/Hz at 1 MHz is obtained.
