Floating Point HUB Adder for RISC-V Sargantana Processor
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Fecha
2023 -
Editorial/Editor
Cornell University -
Palabras clave
Hardware -
Resumen
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their designs currently. In this paper we present a tailored floating point HUB adder that has been implemented in the Sargantana RISC-V processor