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dc.contributor.authorHormigo-Jimenez, Marco
dc.contributor.authorHormigo-Aguilar, Javier 
dc.date.accessioned2023-12-12T12:39:27Z
dc.date.available2023-12-12T12:39:27Z
dc.date.created2023
dc.date.issued2023
dc.identifier.citationHigh-Throughput DTW accelerator with minimum area in AMD FPGA by HLS," 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), Málaga, Spain, 2023, pp. 1-6, doi: 10.1109/DCIS58620.2023.10335963es_ES
dc.identifier.urihttps://hdl.handle.net/10630/28260
dc.description.abstractDynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is extensively used in many machine learning algorithms, especially for pattern recognition and classification. U nfortunately, i t h as a q uadratic complexity, which results in very high computational costs. Furthermore, its data dependency made it also very difficult t o parallelize. Special attention has been paid to computing DTW on the edge, as a way to reduce the load of communication on Internet-of- Thing applications. In this work, we propose a minimum area implementation of the DTW algorithm in AMD FPGAs with optimal use of the resources. That is achieved by maximizing the use time of the resources and taking advantage of the inner structure of the AMD FPGAs. This architecture could be used in small devices or as a base for a multi-core implementation with very high-throughput.es_ES
dc.description.sponsorshipMCIN/AEI/10.13039/501100011033and European Union Next Generation EU/PRTR under Project TED2021- 131527B-I00; by the Fondo Europeo de Desarrollo Regional (UMA20-FEDERJA-059); and by AMD™(Xilinx™) University Program Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech.es_ES
dc.language.isoenges_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectMatrices lógicas programables por el usuarioes_ES
dc.subjectAlgoritmos computacionaleses_ES
dc.subjectCircuitos digitaleses_ES
dc.subject.otherDynamic time warpinges_ES
dc.subject.otherHLS implementationes_ES
dc.subject.otherInterleavinges_ES
dc.subject.otherFPGA accelerationes_ES
dc.titleHigh-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.es_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.centroE.T.S.I. Informáticaes_ES
dc.relation.eventtitle2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)es_ES
dc.relation.eventplaceMálaga, Spaines_ES
dc.relation.eventdateNoviembre del 2023es_ES


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