Listar AC - Artículos por título
Mostrando ítems 22-41 de 65
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Fast HUB Floating-point Adder for FPGA
(2018-10-17)Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
Fisher Motion Descriptor for Multiview Gait Recognition.
(World Scientific, 2017)This paper aims to identify individuals by analyzing their gait using motion descriptors based on densely sampled short-term trajectories, instead of traditional binary silhouettes. The approach leverages advanced people ... -
Floating Point HUB Adder for RISC-V Sargantana Processor
(Cornell University, 2023)HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their ... -
Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures
(IEEE Transactions on Computers, 2021-12)Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in ... -
Hardware Signature Designs to Deal With Asymmetry in Transactional Data Sets
(IEEE, 2013)Transactional Memory (TM) systems must track memory accesses made by concurrent transactions in order to detect conflicts. Many TM implementations use signatures for this purpose, which summarize reads and writes in ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
(Springer, 2021-12-02)This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
(Springer, 2022-03)This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ... -
High-Throughput FPGA Implementation of QR Decomposition
(2015-09-17)This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ... -
HUB meets posit: arithmetic units implementation
(IEEE, 2023)The posit (TM) format was introduced in 2017 as an alternative to replacing the widespread IEEE 754. Posit arithmetic provides reproducible results across platforms and possesses tapered accuracy, among other improvemen ... -
Improving Hardware Transactional Memory Parallelization of Computational Geometry Algorithms Using Privatizing Transactions.
(Elsevier, 2019-05-06)Hardware transactional memory is a new parallel programming paradigm supported by current commercial multiprocessors. This paradigm provides optimistic concurrency and overcomes some of the problems associated with classical ... -
Inventory control for a non-stationary demand perishable product: comparing policies and solution methods
(2018-03-02)This paper summarizes our findings with respect to order policies for an inventory control problem for a perishable product with a maximum fixed shelf life in a periodic review system, where chance constraints play a role. ... -
Irregular alignment of arbitrarily long DNA sequences on GPU
(Springer Nature, 2022-12-22)The use of Graphics Processing Units to accelerate computational applications is increasingly being adopted due to its affordability, flexibility and performance. However, achieving top performance comes at the price of ... -
Lazy Irrevocability for Best-Effort Transactional Memory Systems
(IEEE, 2017)IBM and Intel now offer commercial systems with Transactional Memory (TM), a programming paradigm whose aim is to facilitate concurrent programming while maximizing parallelism. These TM systems are implemented in hardware ... -
Leveraging Irrevocability to Deal with Signature Saturation in Hardware Transactional Memory
(Springer, 2017)In hardware transactional memory, signatures have been proposed to keep track of memory locations accessed in a transaction to help conflict detection. Generally, signatures are implemented as Bloom filters that suffer ... -
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
(Elsevier, 2022-03)The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target ... -
Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest
(IEEE, 2016)This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ... -
Mejorando el rendimiento de la memoria transaccional para aplicaciones irregulares
(2018-11-15)La Memoria Transaccional (TM) ofrece un modelo de ejecución concurrente optimista en arquitecturas multinúcleo, permitiendo a los programadores extraer paralelismo cuando la información de las dependencias de datos no está ... -
MgO-containing porous carbon spheres derived from magnesium lignosulfonate as sustainable basic catalysts
(Elsevier, 2022-11-26)The presence of alkalis in lignosulfonate allows an easy preparation of sustainable MgO-containing carbon catalysts with surface basicity by carbonization of magnesium lignosulfonate and/or further partial gasification of ... -
miRNA as biomarker in lung cancer
(Springer Nature, 2023-08-29)Lung cancer has a high prevalence and mortality due to its late diagnosis and limited treatment, so it is essential to find biomarkers that allow a faster diagnosis and improve the survival of these patients. In this sense, ...