Listar Arquitectura de Computadores - (AC) por título
Mostrando ítems 84-103 de 183
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High performance computing in the cloud
(UMA Editorial, 2017-06-14)The numerous technological advances in data acquisition techniques allow the massive production of enormous amounts of data in diverse fields such as astronomy, health and social networks. Nowadays, only a small part of ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
Villalba-Moreno, Julio
; Hormigo-Aguilar, Javier (Springer, 2021-12-02)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2022-03)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ... -
High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.
Dynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is ... -
High-Throughput FPGA Implementation of QR Decomposition
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ... -
HPC Accelerators with 3D Memory
Ujaldon-Martínez, Manuel (2016-09-13)
After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have con- quered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. ... -
HUB meets posit: arithmetic units implementation
Murillo, Raul; Hormigo-Aguilar, Javier; del Barrio, Alberto A.; Botella, Guillermo (IEEE, 2023)
The posit (TM) format was introduced in 2017 as an alternative to replacing the widespread IEEE 754. Posit arithmetic provides reproducible results across platforms and possesses tapered accuracy, among other improvemen ... -
iDA: Preservando el acceso a bases de datos a muy largo plazo.
El proyecto iDA (Immortal Database Accesss) tiene como objetivo el ofrecer una visión general de las posibilidades tecnológicas para la preservación de los sistemas informáticos desmantelados (decommissioned) y los datos ... -
Implementaciones paralelas para un problema de control de inventarios de productos perecederos
Gutiérrez-Alcoba, Alejandro; Hendrix, Eligius María Theodorus; García-Fernández, Inmaculada; Ortega, Gloria L. (2015-10-05)
En este trabajo se analizan y eval uan dos implementaciones de un algoritmo de optimizaci on para un problema de control de inventarios de productos perecederos. Las implementaciones se han llevado a cabo utilizando ... -
Improvements in Hardware Transactional Memory for GPU Architectures
Villegas Fernández, Alejandro; Asenjo-Plaza, Rafael; González-Navarro, María Ángeles; Plata-González, Óscar Guillermo (2016-07-20)
In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of ... -
Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ... -
Improving Transactional Memory Performance for Irregular Applications
Pedrero-Luque, Manuel; Gutiérrez-Carrasco, Eladio Damián; Romero-Montiel, Sergio; Plata-González, Óscar Guillermo (2015-06-11)
Transactional memory (TM) offers optimistic concurrency support in modern multicore archi- tectures, helping the programmers to extract parallelism in irregular applications when data dependence information is not available ... -
Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Zapata, Emilio L.; Plata-González, Óscar Guillermo (Springer International Publishing, 2016-08-24)
Current industry proposals for Hardware Transactional Memory (HTM) focus on best-effort solutions (BE-HTM) where hardware limits are imposed on transactions. These designs may show a significant performance degradation ... -
Inteligencia Artificial en biomedicina
(UMA Editorial, 2024)En esta tesis doctoral vamos a realizar un recorrido por los distintos pasos del flujo de trabajo de la Inteligencia Artificial aplicado a la biomedicina. Desde la recolección de datos y su etiquetado, su análisis mediante ... -
Introduccion a OpenCL
(2014-05-12)Este curso ofrecerá una introducción a OpenCL en el contexto de C y sus aplicaciones científicas. OpenCL proporciona el acceso a estos nuevos recursos computacionales y una forma coherente de utilizarlos para resolver ... -
An Introduction to Intel Threading Building Blocks and its Support for Heterogeneous Programming
Asenjo-Plaza, Rafael; Cownie, Jim; Fedotov, Aleksei (2018-03-12)
Due to energy constraints, high performance computing platforms are becoming increasingly heterogeneous, achieving greater performance per watt through the use of hardware that is tuned to specific computational kernels ... -
Inventory control for a non-stationary demand perishable product: comparing policies and solution methods
Hendrix, Eligius María Theodorus; Pauls-Worm, Karin G.J. (2018-03-02)
This paper summarizes our findings with respect to order policies for an inventory control problem for a perishable product with a maximum fixed shelf life in a periodic review system, where chance constraints play a role. ... -
Irregular alignment of arbitrarily long DNA sequences on GPU
Perez-Wohlfeil, Esteban; Trelles-Salazar, Oswaldo Rogelio; Guil-Mata, Nicolás (Springer Nature, 2022-12-22)
The use of Graphics Processing Units to accelerate computational applications is increasingly being adopted due to its affordability, flexibility and performance. However, achieving top performance comes at the price of ... -
Irrevocabilidad Relajada para Memoria Transaccional Hardware
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Zapata, Emilio L.; Plata-González, Óscar Guillermo (2016-09-20)
Los sistemas comerciales que ofrecen memoria transaccional (TM) implementan un sistema hardware best-effort (BE-HTM) con limitaciones. Es necesario programar un fallback software basado en cerrojos para asegurar el progreso ... -
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
Rodríguez-Moreno, Andrés; González-Navarro, María Ángeles; Nikov, Kris; Nunez-Yanez, José; Gran-Tejero, Rubén; Suárez Gracia, Darío; Asenjo-Plaza, Rafael[et al.] (Elsevier, 2022-03)
The trend for heterogeneous embedded systems is the integration of accelerators and general-purpose CPU cores on the same die. In these integrated architectures, like the Zynq UltraScale+ board (CPU+FPGA) that we target ...