Listar Arquitectura de Computadores - (AC) por título
Mostrando ítems 71-90 de 183
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Gait recognition applying Incremental learning
Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolás
; Schmid, Cordelia; Alahari, Karteek (2019-11-25)
when new knowledge needs to be included in a classifier, the model is retrained from scratch using a huge training set that contains all available information of both old and new knowledge. However, in this talk, we present ... -
Gait recognition from multiple view-points
(UMA Editorial, 2018-11-15)Arquitectura de Computadores Resumen tesis: La identificación automática de personas está ganando mucha importancia en los últimos años ya que se puede aplicar en entornos que deben ser seguros (aeropuertos, centrales ... -
Generating order policies by SDP: non-stationary demand and service level constraints
Pauls-Worm, Karin G.J.; Hendrix, Eligius María Theodorus (2015-07-06)
Inventory control implies dynamic decision making. Therefore, dynamic programming seems an appropriate approach to look for order policies. For finite horizon planning, the implementation of service level constraints ... -
Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures
Qureshi, Yasir Mahmood; Herruzo-Ruiz, José Manuel; Zapater, Marina; Olcoz, Katzalin; González-Navarro, Sonia; Óscar, Plata; Atienza, David[et al.] (IEEE Transactions on Computers, 2021-12)
Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in ... -
Genome sequence alignment in processing-In-memory architectures
Herruzo-Ruiz, José Manuel (UMA Editorial, 2021-01-27)
La combinación de la aparición de un cuello de botella en el acceso a los datos y la creciente importancia de las aplicaciones de procesamiento intensivo de datos, muy limitadas por el sistema de memoria, crea un importante ... -
GPGPU: Challenges ahead
Ujaldon-Martínez, Manuel (2015-11-13)
Evolución, presente y futuro de la memoria DRAM del computador desde el punto de vista de los procesadores gráficos actuales, y su contribución presente y futura para la aceleración de aplicaciones científicas. -
GPUs for high performance computing, Deep learning and beyond
Ujaldon-Martínez, Manuel (2019-10-24)
After an impressive evolution within the last decade, Graphics Processing Units (GPUs) constitute nowadays a solid trend to accelerate scientific applications. This talk unveils the GPU architecture from an ... -
GPUs para HPC: Logros y perspectivas futuras
Ujaldon-Martínez, Manuel (2013-10-18)
Hace una década comenzábamos a mejorar las primeras aplicaciones científicas en GPUs utilizando Cg y OpenGL. Ahora CUDA y OpenCL han tomado el relevo, marcando un ritmo vertiginoso en la aceleración de códigos procedentes ... -
Hardware support for Local Memory Transactions on GPU Architectures
Villegas Fernández, Alejandro; González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Plata-González, Óscar Guillermo; Ubal, Rafael; Kaeli, David[et al.] (2015-06-26)
Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT ... -
Hardware support for scratchpad memory transactions on GPU architectures
Villegas Fernández, Alejandro; Asenjo-Plaza, Rafael; González-Navarro, María Ángeles; Plata-González, Óscar Guillermo; Ubal, Rafael; Kaeli, David[et al.] (Springer, 2017-08-29)
Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL ... -
Harnessing the power of reconfigurable computing platforms
(2016-11-17)Reconfigurable computing platforms are emerging as the most promising architectures to design general purpose systems due to their high flexibility and power efficiency. This talk will discuss several aspects of FPGA ... -
Heuristics for Longest Edge Selection in Simplicial Branch and Bound
Herrera, Juan F.R.; Casado, Leocadio G.; Hendrix, Eligius María Theodorus; García-Fernández, Inmaculada (2015-07-06)
Simplicial partitions are suitable to divide a bounded area in branch and bound. In the iterative re nement process, a popular strategy is to divide simplices by their longest edge, thus avoiding needle-shaped simplices. ... -
High Performance Computing for Genomics
(UMA Editorial, 2023)With the thrive of data acquisition methods, computerized research has become increasingly more common. However, in order to match the huge data-processing demands, the design of new algorithms along with their optimization ... -
High performance computing in the cloud
(UMA Editorial, 2017-06-14)The numerous technological advances in data acquisition techniques allow the massive production of enormous amounts of data in diverse fields such as astronomy, health and social networks. Nowadays, only a small part of ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2021-12-02)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2022-03)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ... -
High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.
Dynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is ... -
High-Throughput FPGA Implementation of QR Decomposition
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ... -
HPC Accelerators with 3D Memory
Ujaldon-Martínez, Manuel (2016-09-13)
After a decade evolving in the High Performance Computing arena, GPU-equipped supercomputers have con- quered the top500 and green500 lists, providing us unprecedented levels of computational power and memory bandwidth. ... -
HUB meets posit: arithmetic units implementation
Murillo, Raul; Hormigo-Aguilar, Javier; del Barrio, Alberto A.; Botella, Guillermo (IEEE, 2023)
The posit (TM) format was introduced in 2017 as an alternative to replacing the widespread IEEE 754. Posit arithmetic provides reproducible results across platforms and possesses tapered accuracy, among other improvemen ...