Listar Arquitectura de Computadores - (AC) por título
Mostrando ítems 68-87 de 207
-
Factorización LU de matrices dispersas en multiprocesadores
Asenjo-Plaza, Rafael
(Universidad de Málaga, Servicio de Publicaciones, 1997)
-
Fast HUB Floating-point Adder for FPGA
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; González-Navarro, Sonia (2018-10-17)
Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
A first step to accelerating fingerprint matching based on deformable minutiae clustering
(2018-07-12)Fingerprint recognition is one of the most used biometric methods for authentication. The identification of a query fingerprint requires matching its minutiae against every minutiae of all the fingerprints of the database. ... -
Fisher Motion Descriptor for Multiview Gait Recognition.
Castro, Francisco M.; Marín Jiménez, Manuel Jesús; Guil-Mata, Nicolás; Muñoz-Salinas, Rafael (World Scientific, 2017)
This paper aims to identify individuals by analyzing their gait using motion descriptors based on densely sampled short-term trajectories, instead of traditional binary silhouettes. The approach leverages advanced people ... -
Floating Point HUB Adder for RISC-V Sargantana Processor
Bandera-Burgueño, Gerardo; Salamero, Javier; Moreto, Miquel; Villalba-Moreno, Julio (Cornell University, 2023)
HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their ... -
Floating Point Square Root under HUB Format
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ... -
FPGA acceleration of bit-true simulations for word-length optimization.
Hormigo-Aguilar, Javier; Caffarena, Gabriel (IEEE, 2021)
The end of Moore's law and the arrival of new highly demanding applications have awakened the interest in exploring different number representation formats and also combining them to implement domain-specific accelerators. ... -
Gait recognition and fall detection with inertial sensors
Delgado-Escaño, Rubén; Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolás (2019-11-26)
In contrast to visual information that is recorded by cameras placed somewhere, inertial information can be obtained from mobile phones that are commonly used in daily life. We present in this talk a general deep learning ... -
Gait recognition applying Incremental learning
Castro, Francisco M.; Marín-Jiménez, Manuel J.; Guil-Mata, Nicolás; Schmid, Cordelia; Alahari, Karteek (2019-11-25)
when new knowledge needs to be included in a classifier, the model is retrained from scratch using a huge training set that contains all available information of both old and new knowledge. However, in this talk, we present ... -
Gait recognition from multiple view-points
(UMA Editorial, 2018-11-15)Arquitectura de Computadores Resumen tesis: La identificación automática de personas está ganando mucha importancia en los últimos años ya que se puede aplicar en entornos que deben ser seguros (aeropuertos, centrales ... -
Generating order policies by SDP: non-stationary demand and service level constraints
Pauls-Worm, Karin G.J.; Hendrix, Eligius María Theodorus (2015-07-06)
Inventory control implies dynamic decision making. Therefore, dynamic programming seems an appropriate approach to look for order policies. For finite horizon planning, the implementation of service level constraints ... -
Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures
Qureshi, Yasir Mahmood; Herruzo-Ruiz, José Manuel; Zapater, Marina; Olcoz, Katzalin; González-Navarro, Sonia; Óscar, Plata; Atienza, David[et al.] (IEEE Transactions on Computers, 2021-12)
Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in ... -
Genome sequence alignment in processing-In-memory architectures
Herruzo-Ruiz, José Manuel (UMA Editorial, 2021-01-27)
La combinación de la aparición de un cuello de botella en el acceso a los datos y la creciente importancia de las aplicaciones de procesamiento intensivo de datos, muy limitadas por el sistema de memoria, crea un importante ... -
GPGPU: Challenges ahead
Ujaldon-Martínez, Manuel (2015-11-13)
Evolución, presente y futuro de la memoria DRAM del computador desde el punto de vista de los procesadores gráficos actuales, y su contribución presente y futura para la aceleración de aplicaciones científicas. -
GPUs for high performance computing, Deep learning and beyond
Ujaldon-Martínez, Manuel (2019-10-24)
After an impressive evolution within the last decade, Graphics Processing Units (GPUs) constitute nowadays a solid trend to accelerate scientific applications. This talk unveils the GPU architecture from an ... -
GPUs para HPC: Logros y perspectivas futuras
Ujaldon-Martínez, Manuel (2013-10-18)
Hace una década comenzábamos a mejorar las primeras aplicaciones científicas en GPUs utilizando Cg y OpenGL. Ahora CUDA y OpenCL han tomado el relevo, marcando un ritmo vertiginoso en la aceleración de códigos procedentes ... -
Hardware Signature Designs to Deal With Asymmetry in Transactional Data Sets
Quislant-del-Barrio, Ricardo; Gutiérrez-Carrasco, Eladio Damián; Plata-González, Óscar Guillermo; López-Zapata, Emilio (IEEE, 2013)
Transactional Memory (TM) systems must track memory accesses made by concurrent transactions in order to detect conflicts. Many TM implementations use signatures for this purpose, which summarize reads and writes in ... -
Hardware support for Local Memory Transactions on GPU Architectures
Villegas Fernández, Alejandro; González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Plata-González, Óscar Guillermo; Ubal, Rafael; Kaeli, David[et al.] (2015-06-26)
Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT ... -
Hardware support for scratchpad memory transactions on GPU architectures
Villegas Fernández, Alejandro; Asenjo-Plaza, Rafael; González-Navarro, María Ángeles; Plata-González, Óscar Guillermo; Ubal, Rafael; Kaeli, David[et al.] (Springer, 2017-08-29)
Graphics Processing Units (GPUs) have become the accelerator of choice for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. Using OpenCL ... -
Harnessing the power of reconfigurable computing platforms
(2016-11-17)Reconfigurable computing platforms are emerging as the most promising architectures to design general purpose systems due to their high flexibility and power efficiency. This talk will discuss several aspects of FPGA ...