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Reproducible SUmmation under HUB Format
| dc.contributor.author | Villalba-Moreno, Julio | |
| dc.contributor.author | Hormigo-Aguilar, Javier | |
| dc.contributor.author | Jaime-Rodríguez, Francisco José | |
| dc.date.accessioned | 2019-06-17T10:15:16Z | |
| dc.date.available | 2019-06-17T10:15:16Z | |
| dc.date.created | 2019-06 | |
| dc.identifier.uri | https://hdl.handle.net/10630/17818 | |
| dc.description | Version diferente del paper presentado en el congreso | en_US |
| dc.description.abstract | Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any carry propagation and saving time and area. In this paper we study the reproducible summation of HUB numbers by using a errorfree vector transformation technique, providing both a specific architecture and the usage of combined HUB/Standard floating point adders to achieve a reproducible result | en_US |
| dc.description.sponsorship | Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | info:eu-repo/semantics/openAccess | en_US |
| dc.subject | Aritmética computacional | en_US |
| dc.subject.other | Reproducible summation | en_US |
| dc.subject.other | HUB format | en_US |
| dc.subject.other | Error-free vector transformation | en_US |
| dc.subject.other | Floating point arithmetic | en_US |
| dc.subject.other | Computer arithmetic | en_US |
| dc.title | Reproducible SUmmation under HUB Format | en_US |
| dc.type | info:eu-repo/semantics/conferenceObject | en_US |
| dc.centro | E.T.S.I. Informática | en_US |
| dc.relation.eventtitle | 2019 IEEE 26TH SYMPOSIUM ON COMPUTER ARITHMETIC | en_US |
| dc.relation.eventplace | Kioto, Japon | en_US |
| dc.relation.eventdate | 10-12 Junio 2019 | en_US |