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Fast HUB Floating-point Adder for FPGA
| dc.contributor.author | Villalba-Moreno, Julio | |
| dc.contributor.author | Hormigo-Aguilar, Javier | |
| dc.contributor.author | González-Navarro, Sonia | |
| dc.date.accessioned | 2018-10-17T08:36:03Z | |
| dc.date.available | 2018-10-17T08:36:03Z | |
| dc.date.created | 2018 | |
| dc.date.issued | 2018-10-17 | |
| dc.identifier.uri | https://hdl.handle.net/10630/16620 | |
| dc.description.abstract | Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point adder for FPGA which greatly improves the speed of previous proposed HUB designs for these devices. Our architecture is based on the double path technique which reduces the execution time since each path works in parallel. We also deal with the implementation of unbiased rounding in the proposed adder. Experimental results are presented showing the goodness of the new HUB adder for FPGA. | en_US |
| dc.description.sponsorship | TIN2016- 80920-R, JA2012 P12-TIC-1692, JA2012 P12-TIC-1470 | en_US |
| dc.language.iso | spa | en_US |
| dc.relation.ispartofseries | IEEE Transactions on Circuits and Systems--II: Express Briefs; | |
| dc.rights | info:eu-repo/semantics/openAccess | en_US |
| dc.subject | Microprocesadores | en_US |
| dc.subject.other | Floating-point (FP) | en_US |
| dc.subject.other | Field-programmable gate array (FPGA) | en_US |
| dc.subject.other | Addition | en_US |
| dc.subject.other | Half-unit biased (HUB) format | en_US |
| dc.subject.other | Unbiased rounding | en_US |
| dc.title | Fast HUB Floating-point Adder for FPGA | en_US |
| dc.type | info:eu-repo/semantics/article | en_US |
| dc.centro | E.T.S.I. Informática | en_US |
| dc.identifier.doi | 10.1109/TCSII.2018.2873194 |