Listar por autor "Hormigo-Aguilar, Javier"
Mostrando ítems 1-20 de 29
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Aceleración de funciones hash mediante FPGAs
(2023)Este trabajo de fin de grado, tiene como objetivo principal, comparar el rendimiento de las funciones hash criptográficas SHA-256 y SHA-512, en las arquitecturas hardware CPU y FPGA. Tiene como propósito secundario, servir ... -
Aceleración de la computación en altas prestaciones mediante FPGA.
(UMA Editorial, 2017-07-06)Actualmente, cada vez es más común ver algoritmos implementados para arquitecturas heterogéneas, en las que se distinguen más de un tipo de elemento procesador. En esta tesis se quieren presentar las increíbles ventajas ... -
Aceleración de simulaciones bit-true para la optimización de anchos de palabra mediante herramientas de síntesis de alto nivel
(2021-12)El propósito del presente trabajo n de grado es proporcionar al diseñador de circuitos digitales un sistema que ejecute la optimización de anchos de palabra a un circuito digital, me diante simulaciones bit-true aceleradas ... -
Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures.
This paper explores new advanced quantization schemes for fast Fourier transform (FFT) architectures. In previous works, FFT quantization has been treated theoretically or with the sole aim of improving accuracy. In this ... -
El autoaprendizaje como competencia central en la enseñanza de fundamentos de computadores.
Hormigo-Aguilar, Javier
(2024)
En este trabajo presentamos la experiencia de abordar el estudio de los fundamentos del computador con una metodología centrada en el alumno. Para ello, las clases magistrales son sustituidas por material didáctico variado, ... -
Control de consumo energético usando Internet of Things
(2020-11-03)Diseño e implementación de un sistema Internet de las Cosas para el hogar, que permite registrar, controlar y calcular el consumo de energía eléctrica de los dispositivos de un hogar. Para realizar esta tarea, se han ... -
Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden
Hormigo-Aguilar, Javier; Rodríguez-Moreno, Andrés (2019-10-11)
The fast evolution of technologies forces teachers to trade content off for self-learning. Project-based learning (PBL) is one of the best ways to promote self-learning and simultaneously boost motivation. In this paper, ... -
Efficient floating-point givens rotation unit
Hormigo-Aguilar, Javier; Muñoz, Sergio (2020-10-23)
High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, ... -
Efficient Floating-Point Representation for Balanced Codes for FPGA Devices
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; Corbera-Peña, Francisco Javier; González, Mario; López-Zapata, Emilio (2013-10-30)
We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ... -
Fast HUB Floating-point Adder for FPGA
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier; González-Navarro, Sonia (2018-10-17)
Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ... -
Floating Point Square Root under HUB Format
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (2017-09-26)
Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ... -
FPGA acceleration of bit-true simulations for word-length optimization.
Hormigo-Aguilar, Javier; Caffarena, Gabriel (IEEE, 2021)
The end of Moore's law and the arrival of new highly demanding applications have awakened the interest in exploring different number representation formats and also combining them to implement domain-specific accelerators. ... -
Guía docente común de las titulaciones de Ingeniero en Electrónica en las universidades andaluzas
Jiménez Tejada, Juan Antonio; Colodro Ruiz, Francisco; Torralba Silgado, Antonio; Parrilla Roure, Luis; Pérez Fernández, José María; Díaz García, Antonio; Rodríguez Bolívar, Salvador; Gámiz Pérez, Francisco; López Villanueva, Juan Antonio; Palma López, Alberto José; López Soler, Juan Manuel; Godoy Medina, Andrés; Palomo Pinto, Rogelio; Hormigo-Aguilar, Javier; Fernández-Ramos, José; Gutiérrez-Carrasco, Eladio Damián; García Ortega, Juan; Peinado-Domínguez, Alberto; Carceller Beltrán, Juan E.; Ramírez Pérez de Inestrosa, Javier; Hidalgo-López, José Antonio; Heredia-Larrubia, Juan Ramón; Vidal-Verdú, Fernando; Romero-Gómez, Luis Felipe; Trenas-Castro, María Antonia; Ríos-Gómez, Francisco Javier; García-Corrales, Celia[et al.] (2006)
El presente documento constituye el resultado del trabajo elaborado de acuerdo con la Convocatoria de Elaboración de Guías Docentes de Titulaciones Andaluzas conforme al Sistema de Créditos Europeos (años 2005/2006) de la ... -
High-Radix Formats for Enhancing Floating-Point FPGA Implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2021-12-02)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ... -
High-radix formats for enhancing floating-point FPGA implementations
Villalba-Moreno, Julio; Hormigo-Aguilar, Javier (Springer, 2022-03)
This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ... -
High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS.
Dynamic Time Warping (DTW) is a dynamic programming algorithm that is known to be one of the best methods to measure the similarities between two signals, even if there are variations in the speed of those. It is ... -
High-Throughput FPGA Implementation of QR Decomposition
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-09-17)
This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are ... -
HUB meets posit: arithmetic units implementation
Murillo, Raul; Hormigo-Aguilar, Javier; del Barrio, Alberto A.; Botella, Guillermo (IEEE, 2023)
The posit (TM) format was introduced in 2017 as an alternative to replacing the widespread IEEE 754. Posit arithmetic provides reproducible results across platforms and possesses tapered accuracy, among other improvemen ... -
Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest
Muñoz, Sergio D.; Hormigo-Aguilar, Javier (2015-06-29)
QR decomposition is a key operation in many current communication systems. This paper shows how to reduce the area of a fixed-point QR decomposition implementation based on Givens rotations by using a new number ... -
Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest
Hormigo-Aguilar, Javier; Villalba-Moreno, Julio (IEEE, 2016)
This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ...