Listar por autor "Villalba-Moreno, Julio"

(2016-07-21)

Half-Unit-Biased format is based on shifting the representation line of the binary numbers by half Unit in the Last Place. The main feature of this format is that the round to nearest is carried out by a simple truncation, ...

Efficient Floating-Point Representation for Balanced Codes for FPGA Devices

; Corbera-Peña, Francisco Javier

; González, Mario; López-Zapata, Emilio

(2013-10-30)

We propose a floating–point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in ...

Fast HUB Floating-point Adder for FPGA

; González-Navarro, Sonia

(2018-10-17)

Several previous publications have shown the area and delay reduction when implementing real number computation using HUB formats for both floating-point and fixed-point. In this paper, we present a HUB floating-point ...

Floating Point HUB Adder for RISC-V Sargantana Processor

Bandera-Burgueño, Gerardo

; Salamero, Javier; Moreto, Miquel; Villalba-Moreno, Julio

(Cornell University, 2023)

HUB format is an emerging technique to improve the hardware and time requirement when round to nearest is needed. On the other hand, RISC-V is a open source ISA that an important number of companies are using in their ...

Floating Point Square Root under HUB Format

(2017-09-26)

Unit-Biased (HUB) is an emerging format based on shifting the representation line of the binary numbers by half unit in the last place. The HUB format is specially relevant for computers where rounding to nearest is ...

High-Radix Formats for Enhancing Floating-Point FPGA Implementations

(Springer, 2021-12-02)

This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point sup port. Since variable shifter implementation ...

High-radix formats for enhancing floating-point FPGA implementations

(Springer, 2022-03)

This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Since variable shifter implementation ...

Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest

(IEEE, 2016)

This paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the ...

New formats for computing with real-numbers under round-to-nearest

(2015-09-17)

In this paper, a new family of formats to deal with real number for applications requiring round to nearest is proposed. They are based on shifting the set of exactly represented numbers which are used in conventional ...

Optimizing DSP Circuits by a New Family of Arithmetic Operators

(2014-11-19)

A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators ...

Reproducible SUmmation under HUB Format

; Jaime-Rodríguez, Francisco José

Floating point reproducibility is a property claimed by programmers and end users. Half-Unit-Biased (HUB) is a new representation format in which the round to nearest is carried out by truncation, preventing any ...

Simplified Floating-Point Units for High Dynamic Range Image and Video Systems

(2015-06-29)

The upcoming arrival of high dynamic range image and video applications to consumer electronics will force the utilization of floating-point numbers on them. This paper shows that introducing a slight modification on ...

Unbiased Rounding for HUB Floating-point Addition