Listar por autor "Vilches Reina, Antonio"
Mostrando ítems 1-6 de 6
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Adaptive Partition Strategies for Loop Parallelism in Heterogeneous Architectures
Vilches Reina, Antonio; Asenjo-Plaza, Rafael
; Corbera-Peña, Francisco Javier; González-Navarro, María Ángeles (2014-07-30)
This paper explores the possibility of efficiently using multicores in conjunction with multiple GPU accelerators under a parallel task programming paradigm. In particular, we address the challenge of extending a ... -
Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM
Romero Moreno, José Carlos; González-Navarro, María Ángeles; Vilches Reina, Antonio; Corbera-Peña, Francisco Javier (Elsevier, 2021-12)
In this work, we study the problem of efficiently executing a state-of-the-art time series algorithm class – SCAMP – on a heterogeneous platform comprised of CPU + High Performance FPGA with integrated HBM (High Bandwidth ... -
Patrón pipeline aplicado a arquitecturas heterogéneas big.LITTLE
Vilches Reina, Antonio; Rodríguez-Moreno, Andrés; González-Navarro, María Ángeles; Corbera-Peña, Francisco Javier; Asenjo-Plaza, Rafael (2015-09-25)
En este trabajo, proponemos una solución para permitir la ejecución de aplicaciones de tipo streaming, que constan de una serie de etapas, sobre arquitecturas heterogéneas con un multicore y una GPU integrada. Para ello, ... -
Pipeline template for streaming applications on heterogeneous chips
Rodríguez, Andrés; González-Navarro, María Ángeles; Asenjo-Plaza, Rafael; Corbera-Peña, Francisco Javier; Vilches Reina, Antonio; Garzarán, María[et al.] (2015-09-07)
We address the problem of providing support for executing single streaming applications implemented as a pipeline of stages that run on heterogeneous chips comprised of several cores and one on-chip GPU. In this paper, ... -
Reducing overheads of dynamic scheduling on heterogeneous chips
Corbera-Peña, Francisco Javier; Rodríguez, Andrés; Asenjo-Plaza, Rafael; González-Navarro, María Ángeles; Vilches Reina, Antonio; Garzarán, María[et al.] (arXiv.org (Cornell University Library), 2015-01-19)
In recent processor development, we have witnessed the integration of GPU and CPUs into a single chip. The result of this integration is a reduction of the data communication overheads. This enables an efficient collaboration ... -
Scheduling strategies for parallel patterns on heterogeneous architectures
(UMA Editorial, 2017)During the last decade, power consumption and energy efficiency have become key aspects in processor design. Nowadays, the power consumption is the principal limitation for further scaling of chip multiprocessors design ...